JTAG-Pins
---------

TDI  Test Data In
TDO  Test Data Out
TMS  Test Mode Select
TCK  Test Clock (rising edge)



Bit Format
----------

Network byte order, MSB first.



Test Access Port (TAP) State Machine
------------------------------------

State               TMS=0               TMS=1
TEST-LOGIC-RESET    RUN-TEST/IDLE       -
RUN-TEST/IDLE       -                   SELECT-DR-SCAN
SELECT-DR-SCAN      CAPTURE-DR          SELECT-IR-SCAN
CAPTURE-DR          SHIFT-DR            EXIT1-DR
SHIFT-DR            -                   EXIT1-DR
EXIT1-DR            PAUSE-DR            UPDATE-DR
PAUSE-DR            -                   EXIT2-DR
EXIT2-DR            SHIFT-DR            UPDATE-DR
UPDATE-DR           RUN-TEST/IDLE       SELECT-DR-SCAN
SELECT-IR-SCAN      CAPTURE-IR          TEST-LOGIC-RESET
CAPTURE-IR          SHIFT-IR            EXIT1-IR
SHIFT-IR            -                   EXIT1-IR
EXIT1-IR            PAUSE-IR            UPDATE-IR
PAUSE-IR            -                   EXIT2-IR
EXIT2-IR            SHIFT-IR            UPDATE-IR
UPDATE-IR           RUN-TEST/IDLE       SELECT-DR-SCAN


When shifting data into DR or IR TMS has to be set when the last bit
is shifted in to get to the next state.



JTAG Registers
--------------

Boundary-Scan Register          3 bits per I/O
Instruction Register            6 bits
BYPASS Register                 1 bit
Identification Register         32 bits
JTAG Configuration Register     32 bits
USERCODE Register               32 bits
User-Defined Registers          Design-specific



Boundary-Scan Instructions
--------------------------

EXTEST      001111  Enables Boundary-Scan EXTEST operation.
SAMPLE      000001  Enables Boundary-Scan SAMPLE operation.
USER1       000010  Access user-defined register 1.
USER2       000011  Access user-defined register 2.
CFG_OUT     000100  Access the configuration bus for readback.
CFG_IN      000101  Access the configuration bus for configuration.
INTEST      000111  Enables Boundary-Scan INTEST operation.
USERCODE    001000  Enables shifting out user code.
IDCODE      001001  Enables shifting out of ID code.
HIGHZ       001010  3-state output pins while enabling BYPASS Register.
JPROGRAM    001011  Equivalent to and has the same effect as PROGRAM.
JSTART      001100  Clocks the startup sequence when Startup clock
                    source is TCK (StartupClk:JtagClk).
JSHUTDOWN   001101  Clocks the shutdown sequence.
ISC_ENABLE  010000  Marks the beginning of ISC configuration.
                    Full shutdown is executed.
ISC_PROGRAM 010001  Enables in-system programming.
ISC_NOOP    010100  No operation.
ISC_READ    010101  Used to read back BBR.



Programming Spartan3e
---------------------

1. Set instruction register to JPROGRAM
2. Set instruction register to CFG_IN
3. Shift the following 24 bytes into the data register:
   sync        sync        command     clear CRC   flush       flush
   0xffffffff, 0xAA995566, 0x30008001, 0x00000007, 0x00000000, 0x00000000
4. Set instruction register to JSHUTDOWN
5. 12 TCK delay cycles
6. Set instruction register to CFG_IN
7. Shift the following 12 bytes into the data register:
   command     assert GHIGH flush
   0x30008001, 0x00000008, 0x00000000
8. Shift the data from file into the data register
   (then goto TAP state TEST_LOGIC_RESET, then RUN_TEST_IDLE)
9. Set instruction register to JSTART
10. 12 TCK delay cycles
11. Set instruction register to BYPASS



See Also
--------

XAPP452  Spartan-3 Advanced Configuration Architecture