/*

  Copyright (C) 2008 Martin Furter <mf@rola.ch>

  This file is part of wbavr.

  wbavr is free software/hardware; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2, or (at your option)
  any later version.

  wbavr is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with wbavr; see the file COPYING.  If not, write to
  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.

==============================================================================*/
/*

wbavr: AVR CPU with Wishbone Interfaces.

*/

// default interrupt vector width (32 interrupts)
`define IRQ_VECT_WIDTH  5

`include "wbavr_wishbone.v"
`include "wbavr_avr.v"

module wbavr(
    // ----------------------------------------------------------------
    // wishbone common
    clk_i,      // clock input
    rst_i,      // reset input (sync)
    // ----------------------------------------------------------------
    // wishbone code bus, 16 bit
    c_adr_o,    // address output
    c_dat_i,    // data input
    c_dat_o,    // data output
    c_cyc_o,    // cycle in progress output
    c_stb_o,    // strobe output
    c_we_o,     // write enable output
    c_ack_i,    // acknowledge input
    c_err_i,    // error input
    c_rty_i,    // retry input
    // c_lock_o, // bus lock output
    // c_sel_o, // 'byte' select output
    // c_tga_o, // adress tag type output
    // c_tgc_o, // cycle tag type output
    // c_tgd_i, // data tag type input
    // c_tgd_o, // data tag type output
    // ----------------------------------------------------------------
    // wishbone data bus, 8 bit
    d_adr_o,    // address output
    d_dat_i,    // data input
    d_dat_o,    // data output
    d_cyc_o,    // cycle in progress output
    d_stb_o,    // strobe output
    d_we_o,     // write enable output
    d_ack_i,    // acknowledge input
    d_err_i,    // error input
    d_rty_i,    // retry input
    // d_lock_o, // bus lock output
    // d_sel_o, // 'byte' select output
    // d_tga_o, // adress tag type output
    // d_tgc_o, // cycle tag type output
    // d_tgd_i, // data tag type input
    // d_tgd_o, // data tag type output
    // ----------------------------------------------------------------
    // avr signals
    avr_clk_o,  // avr clock output
    irq_vect_i, // interrupt vector input (0 = no interrupt)
    irq_ack_o,  // acknowledge when interrupt starts executing
    wdr_o       // watchdog reset output
);

// support 2^irq_vect_width interrupts including reset
// (use 'defparam avr0.irq_vect_width = 4' or 'wbavr #(4) avr0(...)')
parameter irq_vect_width = `IRQ_VECT_WIDTH;

// wishbone common
input           clk_i;
input           rst_i;
// wishbone code bus, 16 bit
output  [15:1]  c_adr_o;
input   [15:0]  c_dat_i;
output  [15:0]  c_dat_o;
output          c_cyc_o;
output          c_stb_o;
output          c_we_o;
input           c_ack_i;
input           c_err_i;
input           c_rty_i;
// wishbone data bus, 8 bit
output  [15:0]  d_adr_o;
input   [7:0]   d_dat_i;
output  [7:0]   d_dat_o;
output          d_cyc_o;
output          d_stb_o;
output          d_we_o;
input           d_ack_i;
input           d_err_i;
input           d_rty_i;
// avr signals
output          avr_clk_o;
input   [irq_vect_width-1:0] irq_vect_i;
output          irq_ack_o;
output          wdr_o;

// internal signals
wire [15:1] avr_c_adr;
wire [15:0] avr_c_dat_rd;
wire [15:0] avr_c_dat_wr;
wire avr_c_rd;
wire avr_c_wr;
wire [15:0] avr_d_adr;
wire [7:0] avr_d_dat_rd;
wire [7:0] avr_d_dat_wr;
wire avr_d_rd;
wire avr_d_wr;


wbavr_wishbone U0(
    // wishbone common
    .wb_clk_i(clk_i),
    .wb_rst_i(rst_i),
    // wishbone code bus, 16 bit
    .wb_c_adr_o(c_adr_o),
    .wb_c_dat_rd_i(c_dat_i),
    .wb_c_dat_wr_o(c_dat_o),
    .wb_c_cyc_o(c_cyc_o),
    .wb_c_stb_o(c_stb_o),
    .wb_c_we_o(c_we_o),
    .wb_c_ack_i(c_ack_i),
    .wb_c_err_i(c_err_i),
    .wb_c_rty_i(c_rty_i),
    // wishbone data bus, 8 bit
    .wb_d_adr_o(d_adr_o),
    .wb_d_dat_rd_i(d_dat_i),
    .wb_d_dat_wr_o(d_dat_o),
    .wb_d_cyc_o(d_cyc_o),
    .wb_d_stb_o(d_stb_o),
    .wb_d_we_o(d_we_o),
    .wb_d_ack_i(d_ack_i),
    .wb_d_err_i(d_err_i),
    .wb_d_rty_i(d_rty_i),
    // avr common
    .avr_clk_o(avr_clk_o),
    // avr code bus
    .avr_c_adr_i(avr_c_adr),
    .avr_c_dat_rd_o(avr_c_dat_rd),
    .avr_c_dat_wr_i(avr_c_dat_wr),
    .avr_c_rd_i(avr_c_rd),
    .avr_c_wr_i(avr_c_wr),
    // avr data bus
    .avr_d_adr_i(avr_d_adr),
    .avr_d_dat_rd_o(avr_d_dat_rd),
    .avr_d_dat_wr_i(avr_d_dat_wr),
    .avr_d_rd_i(avr_d_rd),
    .avr_d_wr_i(avr_d_wr)
);

wbavr_avr #(
    .irq_vect_width(irq_vect_width)
) U1(
    // avr common
    .avr_clk_i(avr_clk_o),
    // avr code bus
    .avr_c_adr_o(avr_c_adr),
    .avr_c_dat_rd_i(avr_c_dat_rd),
    .avr_c_dat_wr_o(avr_c_dat_wr),
    .avr_c_rd_o(avr_c_rd),
    .avr_c_wr_o(avr_c_wr),
    // avr data bus
    .avr_d_adr_o(avr_d_adr),
    .avr_d_dat_rd_i(avr_d_dat_rd),
    .avr_d_dat_wr_o(avr_d_dat_wr),
    .avr_d_rd_o(avr_d_rd),
    .avr_d_wr_o(avr_d_wr),
    // avr interrupts
    .avr_irq_vect_i(irq_vect_i),
    .avr_irq_ack_o(irq_ack_o),
    // avr misc
    .avr_wdr_o(wdr_o)
);

endmodule