`include "wbavr_gpregs.v"

module wbavr_gpregs_tb();

reg             clock;
reg     [4:0]   rd_adr_0;
wire    [7:0]   rd_data_0;
reg     [4:0]   rd_adr_1;
wire    [7:0]   rd_data_1;
reg             wr_enable_0;
reg     [4:0]   wr_adr_0;
reg     [7:0]   wr_data_0;
reg             wr_enable_1;
reg     [4:0]   wr_adr_1;
reg     [7:0]   wr_data_1;
wire            wr_conflict;

reg     [7:0]   rd_data_0_exp;
reg     [7:0]   rd_data_1_exp;
reg             wr_conflict_exp;
wire            fail;
integer         failcount;

`define CHECK check( fail, failcount );
task check;
    input fail;
    inout failcount;
    integer failcount;
    begin
        if( fail )
            begin
                failcount = failcount + 1;
                $display(
                    "%6g:  %2h %2h (%2h) %2h %2h (%2h) %b(%b) %b",
                    $time,
                    rd_adr_0, rd_data_0, rd_data_0_exp,
                    rd_adr_1, rd_data_1, rd_data_1_exp,
                    wr_conflict, wr_conflict_exp,
                    fail
                );
            end
    end
endtask

initial
    begin
        $dumpfile( "wbavr_gpregs_tb.vcd" );
        $dumpvars( 1 );
        failcount = 0;
        clock = 0;
        rd_adr_0 = 0;
        rd_adr_1 = 0;
        wr_enable_0 = 0;
        wr_adr_0 = 0;
        wr_data_0 = 0;
        wr_enable_1 = 0;
        wr_adr_1 = 0;
        wr_data_1 = 0;
        wr_conflict_exp = 0;
        #10
        wr_enable_0 = 1; wr_adr_0 = 0; wr_data_0 = 8'h80;
        wr_enable_1 = 1; wr_adr_1 = 1; wr_data_1 = 8'h81;
        wr_conflict_exp = 0;
        #10
        rd_adr_0 = 0; rd_data_0_exp = 8'h80;
        rd_adr_1 = 1; rd_data_1_exp = 8'h81;
        wr_enable_0 = 1; wr_adr_0 = 2; wr_data_0 = 8'h82;
        wr_enable_1 = 1; wr_adr_1 = 3; wr_data_1 = 8'h83;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 2; rd_data_0_exp = 8'h82;
        rd_adr_1 = 3; rd_data_1_exp = 8'h83;
        wr_enable_0 = 1; wr_adr_0 = 4; wr_data_0 = 8'h84;
        wr_enable_1 = 1; wr_adr_1 = 5; wr_data_1 = 8'h85;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 4; rd_data_0_exp = 8'h84;
        rd_adr_1 = 5; rd_data_1_exp = 8'h85;
        wr_enable_0 = 1; wr_adr_0 = 6; wr_data_0 = 8'h86;
        wr_enable_1 = 1; wr_adr_1 = 7; wr_data_1 = 8'h87;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 6; rd_data_0_exp = 8'h86;
        rd_adr_1 = 7; rd_data_1_exp = 8'h87;
        wr_enable_0 = 1; wr_adr_0 = 8; wr_data_0 = 8'h88;
        wr_enable_1 = 1; wr_adr_1 = 9; wr_data_1 = 8'h89;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 8; rd_data_0_exp = 8'h88;
        rd_adr_1 = 9; rd_data_1_exp = 8'h89;
        wr_enable_0 = 1; wr_adr_0 = 10; wr_data_0 = 8'h8A;
        wr_enable_1 = 1; wr_adr_1 = 11; wr_data_1 = 8'h8B;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 10; rd_data_0_exp = 8'h8A;
        rd_adr_1 = 11; rd_data_1_exp = 8'h8B;
        wr_enable_0 = 1; wr_adr_0 = 12; wr_data_0 = 8'h8C;
        wr_enable_1 = 1; wr_adr_1 = 13; wr_data_1 = 8'h8D;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 12; rd_data_0_exp = 8'h8C;
        rd_adr_1 = 13; rd_data_1_exp = 8'h8D;
        wr_enable_0 = 1; wr_adr_0 = 14; wr_data_0 = 8'h8E;
        wr_enable_1 = 1; wr_adr_1 = 15; wr_data_1 = 8'h8F;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 14; rd_data_0_exp = 8'h8E;
        rd_adr_1 = 15; rd_data_1_exp = 8'h8F;
        wr_enable_0 = 1; wr_adr_0 = 16; wr_data_0 = 8'h90;
        wr_enable_1 = 1; wr_adr_1 = 17; wr_data_1 = 8'h91;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 16; rd_data_0_exp = 8'h90;
        rd_adr_1 = 17; rd_data_1_exp = 8'h91;
        wr_enable_0 = 1; wr_adr_0 = 18; wr_data_0 = 8'h92;
        wr_enable_1 = 1; wr_adr_1 = 19; wr_data_1 = 8'h93;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 18; rd_data_0_exp = 8'h92;
        rd_adr_1 = 19; rd_data_1_exp = 8'h93;
        wr_enable_0 = 1; wr_adr_0 = 20; wr_data_0 = 8'h94;
        wr_enable_1 = 1; wr_adr_1 = 21; wr_data_1 = 8'h95;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 20; rd_data_0_exp = 8'h94;
        rd_adr_1 = 21; rd_data_1_exp = 8'h95;
        wr_enable_0 = 1; wr_adr_0 = 22; wr_data_0 = 8'h96;
        wr_enable_1 = 1; wr_adr_1 = 23; wr_data_1 = 8'h97;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 22; rd_data_0_exp = 8'h96;
        rd_adr_1 = 23; rd_data_1_exp = 8'h97;
        wr_enable_0 = 1; wr_adr_0 = 24; wr_data_0 = 8'h98;
        wr_enable_1 = 1; wr_adr_1 = 25; wr_data_1 = 8'h99;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 24; rd_data_0_exp = 8'h98;
        rd_adr_1 = 25; rd_data_1_exp = 8'h99;
        wr_enable_0 = 1; wr_adr_0 = 26; wr_data_0 = 8'h9A;
        wr_enable_1 = 1; wr_adr_1 = 27; wr_data_1 = 8'h9B;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 26; rd_data_0_exp = 8'h9A;
        rd_adr_1 = 27; rd_data_1_exp = 8'h9B;
        wr_enable_0 = 1; wr_adr_0 = 28; wr_data_0 = 8'h9C;
        wr_enable_1 = 1; wr_adr_1 = 29; wr_data_1 = 8'h9D;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 28; rd_data_0_exp = 8'h9C;
        rd_adr_1 = 29; rd_data_1_exp = 8'h9D;
        wr_enable_0 = 1; wr_adr_0 = 30; wr_data_0 = 8'h9E;
        wr_enable_1 = 1; wr_adr_1 = 31; wr_data_1 = 8'h9F;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 30; rd_data_0_exp = 8'h9E;
        rd_adr_1 = 31; rd_data_1_exp = 8'h9F;
        wr_enable_0 = 1; wr_adr_0 = 0; wr_data_0 = 8'hFF;
        wr_enable_1 = 1; wr_adr_1 = 0; wr_data_1 = 8'h00;
        wr_conflict_exp = 1;
        #6
        `CHECK
        #4
        rd_adr_0 = 0; rd_data_0_exp = 8'hFF;
        rd_adr_1 = 4; rd_data_1_exp = 8'h84;
        wr_enable_0 = 1; wr_adr_0 = 5; wr_data_0 = 8'h5A;
        wr_enable_1 = 0; wr_adr_1 = 5; wr_data_1 = 8'hA5;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 5; rd_data_0_exp = 8'h5A;
        rd_adr_1 = 3; rd_data_1_exp = 8'h83;
        wr_enable_0 = 0; wr_adr_0 = 7; wr_data_0 = 8'h5A;
        wr_enable_1 = 1; wr_adr_1 = 7; wr_data_1 = 8'hA5;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 7; rd_data_0_exp = 8'hA5;
        rd_adr_1 = 13; rd_data_1_exp = 8'h8D;
        wr_enable_0 = 0; wr_adr_0 = 13; wr_data_0 = 8'h5A;
        wr_enable_1 = 0; wr_adr_1 = 15; wr_data_1 = 8'hA5;
        wr_conflict_exp = 0;
        #6
        `CHECK
        #4
        rd_adr_0 = 13; rd_data_0_exp = 8'h8D;
        rd_adr_1 = 15; rd_data_1_exp = 8'h8F;
        #6
        `CHECK
        #4
        $display( "wbavr_gpregs_tb:" );
        if( failcount == 0 )
            $display( "  PASSED" );
        else
            $display( "  FAILED: %d failures", failcount );
        #10 $finish;
    end

always
    begin
        #5 clock = ~clock;
    end

wbavr_gpregs U0(
    .clk_i(clock),
    .rd_adr_0_i(rd_adr_0),
    .rd_data_0_o(rd_data_0),
    .rd_adr_1_i(rd_adr_1),
    .rd_data_1_o(rd_data_1),
    .wr_enable_0_i(wr_enable_0),
    .wr_adr_0_i(wr_adr_0),
    .wr_data_0_i(wr_data_0),
    .wr_enable_1_i(wr_enable_1),
    .wr_adr_1_i(wr_adr_1),
    .wr_data_1_i(wr_data_1),
    .wr_conflict_o(wr_conflict)
);

assign fail = |{ rd_data_0 != rd_data_0_exp,
                 rd_data_1 != rd_data_1_exp,
                 wr_conflict != wr_conflict_exp };

endmodule