`include "wbavr_wishbone.v"
`include "wbavr_consts.v"

module wbavr_wishbone_tb();

// wishbone common
reg             wb_clk_i;
reg             wb_rst_i;
// wishbone code bus, 16 bit
wire    [15:1]  wb_c_adr_o;
reg     [15:0]  wb_c_dat_rd_i;
wire    [15:0]  wb_c_dat_wr_o;
wire            wb_c_cyc_o;
wire            wb_c_stb_o;
wire            wb_c_we_o;
reg             wb_c_ack_i;
reg             wb_c_err_i;
reg             wb_c_rty_i;
// wishbone data bus, 8 bit
wire    [15:0]  wb_d_adr_o;
reg     [7:0]   wb_d_dat_rd_i;
wire    [7:0]   wb_d_dat_wr_o;
wire            wb_d_cyc_o;
wire            wb_d_stb_o;
wire            wb_d_we_o;
reg             wb_d_ack_i;
reg             wb_d_err_i;
reg             wb_d_rty_i;
// avr clock
wire            avr_clk_o;
// avr code bus
reg     [15:1]  avr_c_adr_i;
reg     [15:0]  avr_c_dat_wr_i;
wire    [15:0]  avr_c_dat_rd_o;
reg             avr_c_rd_i;
reg             avr_c_wr_i;
// avr data bus
reg     [15:0]  avr_d_adr_i;
reg     [7:0]   avr_d_dat_wr_i;
wire    [7:0]   avr_d_dat_rd_o;
reg             avr_d_rd_i;
reg             avr_d_wr_i;

// wishbone code bus, 16 bit
reg     [15:1]  wb_c_adr_o_exp;
reg     [15:0]  wb_c_dat_wr_o_exp;
reg             wb_c_cyc_o_exp;
reg             wb_c_stb_o_exp;
reg             wb_c_we_o_exp;
// wishbone data bus, 8 bit
reg     [15:0]  wb_d_adr_o_exp;
reg     [7:0]   wb_d_dat_wr_o_exp;
reg             wb_d_cyc_o_exp;
reg             wb_d_stb_o_exp;
reg             wb_d_we_o_exp;
// avr clock
reg             avr_clk_o_exp;
// avr code bus
reg     [15:0]  avr_c_dat_rd_o_exp;
// avr data bus
reg     [7:0]   avr_d_dat_rd_o_exp;

wire    [12:0]  fail;
integer         failcount;

`define CHECK check( fail, failcount );
task check;
    input [12:0] fail;
    inout failcount;
    integer failcount;
    begin
        if( |{ fail } != 0 )
            begin
                failcount = failcount + 1;
                $display( "%6g:  %b", $time, fail );
                if( fail[12] )
                    begin
                        $display(
                            "  wb_c_adr_o: %2h %2h",
                            wb_c_adr_o, wb_c_adr_o_exp
                        );
                    end
                if( fail[11] )
                    begin
                        $display(
                            "  wb_c_dat_wr_o: %2h %2h",
                            wb_c_dat_wr_o, wb_c_dat_wr_o_exp
                        );
                    end
                if( fail[10] )
                    begin
                        $display(
                            "  wb_c_cyc_o: %2h %2h",
                            wb_c_cyc_o, wb_c_cyc_o_exp
                        );
                    end
                if( fail[9] )
                    begin
                        $display(
                            "  wb_c_stb_o: %2h %2h",
                            wb_c_stb_o, wb_c_stb_o_exp
                        );
                    end
                if( fail[8] )
                    begin
                        $display(
                            "  wb_c_we_o: %2h %2h",
                            wb_c_we_o, wb_c_we_o_exp
                        );
                    end
                if( fail[7] )
                    begin
                        $display(
                            "  wb_d_adr_o: %2h %2h",
                            wb_d_adr_o, wb_d_adr_o_exp
                        );
                    end
                if( fail[6] )
                    begin
                        $display(
                            "  wb_d_dat_wr_o: %2h %2h",
                            wb_d_dat_wr_o, wb_d_dat_wr_o_exp
                        );
                    end
                if( fail[5] )
                    begin
                        $display(
                            "  wb_d_cyc_o: %2h %2h",
                            wb_d_cyc_o, wb_d_cyc_o_exp
                        );
                    end
                if( fail[4] )
                    begin
                        $display(
                            "  wb_d_stb_o: %2h %2h",
                            wb_d_stb_o, wb_d_stb_o_exp
                        );
                    end
                if( fail[3] )
                    begin
                        $display(
                            "  wb_d_we_o: %2h %2h",
                            wb_d_we_o, wb_d_we_o_exp
                        );
                    end
                if( fail[2] )
                    begin
                        $display(
                            "  avr_clk_o: %2h %2h",
                            avr_clk_o, avr_clk_o_exp
                        );
                    end
                if( fail[1] )
                    begin
                        $display(
                            "  avr_c_dat_rd_o: %2h %2h",
                            avr_c_dat_rd_o, avr_c_dat_rd_o_exp
                        );
                    end
                if( fail[0] )
                    begin
                        $display(
                            "  avr_d_dat_rd_o: %2h %2h",
                            avr_d_dat_rd_o, avr_d_dat_rd_o_exp
                        );
                    end
            end
    end
endtask

initial
    begin
        $dumpfile( "wbavr_wishbone_tb.vcd" );
        $dumpvars( 1 );
        failcount = 0;
        // wishbone common
        wb_clk_i = 0;
        wb_rst_i = 1;
        // wishbone code bus, 16 bit
        wb_c_dat_rd_i = 0;
        wb_c_ack_i = 0;
        wb_c_err_i = 0;
        wb_c_rty_i = 0;
        // wishbone data bus, 8 bit
        wb_d_dat_rd_i = 0;
        wb_d_ack_i = 0;
        wb_d_err_i = 0;
        wb_d_rty_i = 0;
        // avr code bus
        avr_c_adr_i = 0;
        avr_c_dat_wr_i = 0;
        avr_c_rd_i = 0;
        avr_c_wr_i = 0;
        // avr data bus
        avr_d_adr_i = 0;
        avr_d_dat_wr_i = 0;
        avr_d_rd_i = 0;
        avr_d_wr_i = 0;

        // wishbone code bus, 16 bit
        wb_c_adr_o_exp = 0;
        wb_c_dat_wr_o_exp = 0;
        wb_c_cyc_o_exp = 0;
        wb_c_stb_o_exp = 0;
        wb_c_we_o_exp = 0;
        // wishbone data bus, 8 bit
        wb_d_adr_o_exp = 0;
        wb_d_dat_wr_o_exp = 0;
        wb_d_cyc_o_exp = 0;
        wb_d_stb_o_exp = 0;
        wb_d_we_o_exp = 0;
        // avr clock
        avr_clk_o_exp = 0;
        // avr code bus
        avr_c_dat_rd_o_exp = 0;
        // avr data bus
        avr_d_dat_rd_o_exp = 0;

        // ------------------------
        // reset
        #10 wb_clk_i = 1'b1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        wb_rst_i = 0;
        #5 `CHECK

        // ------------------------
        // no bus access
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        // $display( "%6g", $time );
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // code bus read
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_c_adr_i = 16'h0102;
        wb_c_adr_o_exp = 16'h0102;
        wb_c_dat_rd_i = 8'h5A;
        avr_c_rd_i = 1;
        wb_c_cyc_o_exp = 1;
        wb_c_stb_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_c_ack_i = 1;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_c_cyc_o_exp = 0;
        wb_c_stb_o_exp = 0;
        avr_c_dat_rd_o_exp = 8'h5A;
        #5 `CHECK
        wb_c_ack_i = 0;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_c_rd_i = 0;
        avr_c_adr_i = 16'h0000;
        wb_c_adr_o_exp = 16'h0000;
        wb_c_dat_rd_i = 8'h00;
        avr_c_dat_rd_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // code bus write
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_c_adr_i = 16'h0204;
        wb_c_adr_o_exp = 16'h0204;
        avr_c_wr_i = 1;
        wb_c_cyc_o_exp = 1;
        wb_c_stb_o_exp = 1;
        wb_c_we_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_c_ack_i = 1;
        avr_c_dat_wr_i = 8'hA5;
        wb_c_dat_wr_o_exp = 8'hA5;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_c_cyc_o_exp = 0;
        wb_c_stb_o_exp = 0;
        wb_c_we_o_exp = 0;
        #5 `CHECK
        wb_c_ack_i = 0;
        wb_c_dat_rd_i = 8'h00;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_c_wr_i = 0;
        avr_c_adr_i = 16'h0000;
        wb_c_adr_o_exp = 16'h0000;
        avr_c_dat_rd_o_exp = 8'h00;
        avr_c_dat_wr_i = 8'h00;
        wb_c_dat_wr_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // data bus read
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_d_adr_i = 16'h0102;
        wb_d_adr_o_exp = 16'h0102;
        wb_d_dat_rd_i = 8'h5A;
        avr_d_rd_i = 1;
        wb_d_cyc_o_exp = 1;
        wb_d_stb_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_d_ack_i = 1;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_d_cyc_o_exp = 0;
        wb_d_stb_o_exp = 0;
        avr_d_dat_rd_o_exp = 8'h5A;
        #5 `CHECK
        wb_d_ack_i = 0;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_d_rd_i = 0;
        avr_d_adr_i = 16'h0000;
        wb_d_adr_o_exp = 16'h0000;
        wb_d_dat_rd_i = 8'h00;
        avr_d_dat_rd_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // data bus write
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_d_adr_i = 16'h0204;
        wb_d_adr_o_exp = 16'h0204;
        avr_d_wr_i = 1;
        wb_d_cyc_o_exp = 1;
        wb_d_stb_o_exp = 1;
        wb_d_we_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_d_ack_i = 1;
        avr_d_dat_wr_i = 8'hA5;
        wb_d_dat_wr_o_exp = 8'hA5;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_d_cyc_o_exp = 0;
        wb_d_stb_o_exp = 0;
        wb_d_we_o_exp = 0;
        #5 `CHECK
        wb_d_ack_i = 0;
        wb_d_dat_rd_i = 8'h00;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_d_wr_i = 0;
        avr_d_adr_i = 16'h0000;
        wb_d_adr_o_exp = 16'h0000;
        avr_d_dat_rd_o_exp = 8'h00;
        avr_d_dat_wr_i = 8'h00;
        wb_d_dat_wr_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // code bus read with delay
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_c_adr_i = 16'h0102;
        wb_c_adr_o_exp = 16'h0102;
        wb_c_dat_rd_i = 8'h5A;
        avr_c_rd_i = 1;
        wb_c_cyc_o_exp = 1;
        wb_c_stb_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_c_ack_i = 1;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_c_cyc_o_exp = 0;
        wb_c_stb_o_exp = 0;
        avr_c_dat_rd_o_exp = 8'h5A;
        #5 `CHECK
        wb_c_ack_i = 0;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_c_rd_i = 0;
        avr_c_adr_i = 16'h0000;
        wb_c_adr_o_exp = 16'h0000;
        wb_c_dat_rd_i = 8'h00;
        avr_c_dat_rd_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        // ------------------------
        // code and data bus read with different delay
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        #5 `CHECK
        avr_c_adr_i = 16'h0102;
        avr_d_adr_i = 16'h0102;
        wb_c_adr_o_exp = 16'h0102;
        wb_d_adr_o_exp = 16'h0102;
        avr_c_rd_i = 1;
        avr_d_rd_i = 1;
        wb_c_cyc_o_exp = 1;
        wb_d_cyc_o_exp = 1;
        wb_c_stb_o_exp = 1;
        wb_d_stb_o_exp = 1;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_c_ack_i = 1;
        wb_c_dat_rd_i = 8'h5A;
        #5 wb_clk_i = 1'b1;
        wb_c_cyc_o_exp = 0;
        wb_c_stb_o_exp = 0;
        avr_c_dat_rd_o_exp = 8'h5A;
        #5 `CHECK
        wb_c_ack_i = 0;
        wb_c_dat_rd_i = 8'h00;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        wb_d_ack_i = 1;
        wb_d_dat_rd_i = 8'h5A;
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        wb_d_cyc_o_exp = 0;
        wb_d_stb_o_exp = 0;
        avr_d_dat_rd_o_exp = 8'h5A;
        #5 `CHECK
        wb_d_ack_i = 0;
        wb_d_dat_rd_i = 8'h00;
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 1;
        avr_c_rd_i = 0;
        avr_d_rd_i = 0;
        avr_c_adr_i = 16'h0000;
        avr_d_adr_i = 16'h0000;
        wb_c_adr_o_exp = 16'h0000;
        wb_d_adr_o_exp = 16'h0000;
        avr_c_dat_rd_o_exp = 8'h00;
        avr_d_dat_rd_o_exp = 8'h00;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK
        #5 wb_clk_i = 1'b1;
        avr_clk_o_exp = 0;
        #5 `CHECK
        #5 wb_clk_i = 1'b0;
        #5 `CHECK

        $display( "wbavr_wishbone_tb:" );
        if( failcount == 0 )
            $display( "  PASSED" );
        else
            $display( "  FAILED: %d failures", failcount );
        #10 $finish;
    end

wbavr_wishbone U0(
    // wishbone common
    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),
    // wishbone code bus, 16 bit
    .wb_c_adr_o(wb_c_adr_o),
    .wb_c_dat_rd_i(wb_c_dat_rd_i),
    .wb_c_dat_wr_o(wb_c_dat_wr_o),
    .wb_c_cyc_o(wb_c_cyc_o),
    .wb_c_stb_o(wb_c_stb_o),
    .wb_c_we_o(wb_c_we_o),
    .wb_c_ack_i(wb_c_ack_i),
    .wb_c_err_i(wb_c_err_i),
    .wb_c_rty_i(wb_c_rty_i),
    // wishbone data bus, 8 bit
    .wb_d_adr_o(wb_d_adr_o),
    .wb_d_dat_rd_i(wb_d_dat_rd_i),
    .wb_d_dat_wr_o(wb_d_dat_wr_o),
    .wb_d_cyc_o(wb_d_cyc_o),
    .wb_d_stb_o(wb_d_stb_o),
    .wb_d_we_o(wb_d_we_o),
    .wb_d_ack_i(wb_d_ack_i),
    .wb_d_err_i(wb_d_err_i),
    .wb_d_rty_i(wb_d_rty_i),
    // avr clock
    .avr_clk_o(avr_clk_o),
    // avr code bus
    .avr_c_adr_i(avr_c_adr_i),
    .avr_c_dat_wr_i(avr_c_dat_wr_i),
    .avr_c_dat_rd_o(avr_c_dat_rd_o),
    .avr_c_rd_i(avr_c_rd_i),
    .avr_c_wr_i(avr_c_wr_i),
    // avr data bus
    .avr_d_adr_i(avr_d_adr_i),
    .avr_d_dat_wr_i(avr_d_dat_wr_i),
    .avr_d_dat_rd_o(avr_d_dat_rd_o),
    .avr_d_rd_i(avr_d_rd_i),
    .avr_d_wr_i(avr_d_wr_i)
);

assign fail = { // 0
                wb_c_adr_o != wb_c_adr_o_exp,
                wb_c_dat_wr_o != wb_c_dat_wr_o_exp,
                wb_c_cyc_o != wb_c_cyc_o_exp,
                wb_c_stb_o != wb_c_stb_o_exp,
                // 4
                wb_c_we_o != wb_c_we_o_exp,
                wb_d_adr_o != wb_d_adr_o_exp,
                wb_d_dat_wr_o != wb_d_dat_wr_o_exp,
                wb_d_cyc_o != wb_d_cyc_o_exp,
                // 8
                wb_d_stb_o != wb_d_stb_o_exp,
                wb_d_we_o != wb_d_we_o_exp,
                avr_clk_o != avr_clk_o_exp,
                avr_c_dat_rd_o != avr_c_dat_rd_o_exp,
                // 12
                avr_d_dat_rd_o != avr_d_dat_rd_o_exp };

endmodule