PACKAGES TSSOP20
 1 PD4    ADC1_A7 TIM2_CH1 TIM2_ETR USART1_CK OPA_OPO / TIM1_ETR_2 TIM1_CH4_3
 2 PD5    ADC1_A5 USART1_TX / TIM2_CH4_3 USART1_RX_2
 3 PD6    ADC1_A6 USART1_RX / TIM2_CH3_3 USART1_TX_2
 4 PD7    TIM2_CH4 CORE_NRST OPA_OPP1 / TIM2_CH4_2 USART1_CK_1 USART1_CK_2
 5 PA1    ADC1_A1 TIM1_CH2 OSC_IN OPA_OPN0 / TIM1_CH2_2
 6 PA2    ADC1_A0 TIM1_CH2N OSC_OUT OPA_OPP0 / ADC1_ETR2_1 TIM1_CH2N_2
 7 VSS    
 8 PD0    OPA_OPN1 TIM1_CH1N / TIM1_CH1N_2 USART1_TX_1 I2C1_SDA_1
 9 VDD    
10 PC0    TIM2_CH3 / TIM1_CH3_1 TIM2_CH3_2 USART1_TX_3 SPI1_NSS_1
11 PC1    I2C1_SDA SPI1_NSS / TIM1_BKIN_1 TIM1_BKIN_3 TIM2_CH4_1 TIM2_CH1_2 TIM2_ETR_2 USART1_RX_3 
12 PC2    TIM1_BKIN USART1_RTS I2C1_SCL / ADC1_ETR_1 TIM1_ETR_3 TIM1_BKIN_2 TIM2_CH2_1 USART1_RTS_1
13 PC3    TIM1_CH3 / TIM1_CH1N_1 TIM1_CH3_2 TIM1_CH1N_3 USART1_CTS_1
14 PC4    ADC1_A2 TIM1_CH4 CORE_MCO / TIM1_CH2N_1 TIM1_CH4_2 TIM1_CH1_3
15 PC5    TIM1_ETR SPI1_SCK / TIM1_CH3_3 TIM1_ETR_1 TIM2_CH1_1 TIM2_ETR_1 USART1_CK_3 I2C1_SCL_2 I2C1_SCL_3 SPI1_SCK_1
16 PC6    SPI1_MOSI / TIM1_CH1_1 TIM1_CH3N_3 USART1_CTS_2 USART1_CTS_3 I2C1_SDA_2 I2C1_SDA_3 SPI1_MOSI_1
17 PC7    SPI1_MISO / TIM1_CH2_1 TIM1_CH2_3 TIM2_CH2_3 USART1_RTS_2 USART1_RTS_3 SPI1_MISO_1
18 PD1    ADC1_ETR2 TIM1_CH3N CORE_SWIO / TIM1_CH3N_1 TIM1_CH3N_2 USART1_RX_1 I2C1_SCL_1
19 PD2    ADC1_A3 TIM1_CH1 / TIM1_CH2N_3 TIM1_CH1_2 TIM2_CH3_1
20 PD3    ADC1_A4 ADC1_ETR TIM2_CH2 USART1_CTS / TIM1_CH4_1 TIM2_CH2_2